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CMOS Fractional-N Synthesizers starts with a comprehensive introduction to general frequency synthesis. Different architectures and synthesizer building blocks are discussed with their relative importance on synthesizer specifications. The process of synthesizer specification derivation is illustrated with the DCS-1800 standard as a general test case.
The book tackles the design of fractional-N synthesizers in CMOS on circuit level as well as system level. The circuit level focuses on high-speed prescaler design up to 12 GHz in CMOS and on fully integrated, low-phase-noise LC-VCO design. High-Q inductor integration and simulation in CMOS is elaborated and flicker noise minimization techniques are presented, ranging from bias point choice to noise filtering techniques.
On a higher level, a systematic design strategy has been developed that trades off all noise contributions and fast dynamics for integrated capacitance (area). Moreover, a theoretical DeltaSigma phase noise analysis is presented, extended with a fast non-linear analysis method to accurately predict the influence of PLL non-linearities on the spectral purity of the DeltaSigma fractional-N frequency synthesizers.
- Sales Rank: #5204470 in Books
- Brand: Bram De Muer
- Published on: 2003-01-31
- Original language: English
- Number of items: 1
- Dimensions: 9.21" h x .75" w x 6.14" l, 1.33 pounds
- Binding: Hardcover
- 677 pages
- CMOS Fractional N Synthesizers Design for High Spectral Purity and Monolithic Integration The Springer International Series in Engineering and Computer Science
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